Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■DMA controller
Target Normal, high resolution
Chip 8237A equivalent
Explanation o PC-9800 (excluding PC-H98, PC-98LT・HA, DB-P1) uses 8237A (equivalent product) as the DMA controller.
The PC-H98 uses a proprietary 32-bit DMA controller that is upwardly compatible with the 8237A.
u PC-98LT・HA, DB-P1 uses V50 built-in DMAU (DMA Unit). The V50 built-in DMAU is a subset of the μPD71071
and is not compatible with the 8237A. The V50HL DMAU used in the DB-P1 also has an 8237A compatible mode,
but it is used in μPD71071 mode.
o The usage of DMA channels differs depending on the model.
[PC-9801 first generation・E・F・M・VM2・VF・U・UV2・UV21]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None *1 | DACK00,DRQ00 signal
1 | Memory refresh | None
2 | Dual-use FD I/F *2 | DACK20, DRQ20 signals (last slot only) (in 1MB I/F mode)
3 | Dual-use FD I/F *2 | DACK30, DRQ30 signals (other than the last slot) (in 640KB I/F mode)
--------------------------+--------------------------------------+---------------
*1: PC-9801F3, M3, and VM4 are used by the built-in SASI I/F.
*2: For dual-use FD I/F, use either CH#2 or 3. Set with DIP SW 3-1,3-2. Channels not used by the built-in FD I/F can be used in expansion slots.
[PC-9801T･DA･DS･DX･CS･FA･FS･FX,PC-9821A series,PC-98GS,PC-98RL(normal)]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | Built-in HD I/F *1 | DACK00,DRQ00 signal
1 | Built-in HD I/F *2 | None
2 | Dual-use FD I/F *3 | None (in 1MB I/F mode)
3 | Dual-use FD I/F *3 | DACK30, DRQ30 signals (in 640KB I/F mode)
--------------------------+--------------------------------------+--------------
*1: When DIP SW 3-3 is OFF, the built-in HD I/F uses CH#0. At this time, CH#0 cannot be used in the expansion slot.
*2: When DIP SW 3-3 is ON, the built-in HD I/F uses CH#1. At this time, CH#0 can be used in the expansion slot.
*3: For dual-use FD I/F, use either CH#2 or 3. Set with DIP SW 3-1,3-2. In 1MB I/F mode, CH#3 can be used as an expansion slot.
[PC-H98 normal mode]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None | DRQ00 signal (C bus, E bus)
1 | Dual-use FD I/F | DRQ10 (E bus)
2 | Dual-use FD I/F *1 | DRQ20 (E bus) (in 1MB I/F mode)
3 | Dual-use FD I/F *1 | DRQ30 signal (C bus, E bus) (in 640KB I/F mode)
4 | None | DRQ40 (E bus)
5 | None | DRQ50 (E bus)
6 | None | DRQ60 (E bus)
--------------------------+--------------------------------------+---------------
*1: For dual-use FD I/F, use either CH#2 or 3. Set with DIP SW 3-1,3-2. Channels not used by the built-in FD I/F can be used in expansion slots.
* The DMA channel to be used for the built-in hard disk and NESA HD I/F can be set by manual setup.
* DMA channel 7 is not available.
[Normal mode for other models]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None *1 | DACK00,DRQ00 signal
1 | None | None
2 | Dual-use FD I/F *1 | None (in 1MB I/F mode)
3 | Dual-use FD I/F *1 | DACK30, DRQ30 signals (in 640KB I/F mode)
--------------------------+--------------------------------------+---------------
*1: For dual-use FD I/F, use either CH#2 or 3. Set with DIP SW 3-1,3-2. In 1MB I/F mode, CH#3 can be used as an expansion slot.
[PC-98XA]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None | DACK00,DRQ00 signal (slots #1, 2, 3, 5 only)
1 | Dual-use FD I/F | DACK10, DRQ10 signal (slot #1 only) *1
2 | None | DACK20, DRQ20 signal (slot #2 only)
3 | None *2 | DACK30, DRQ30 signal (Slots #3, 4, 5 only)
--------------------------+--------------------------------------+---------------
*1: Slot #1 is equipped with a dual-purpose FD I/F as standard.
*2: PC-98XA model 3･31 uses built-in SASI I/F.
[PC-98XL・XL^2 High resolution mode]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None *1 | DACK00,DRQ00 signal
1 | Dual-use FD I/F | None
2 | None | None
3 | None | DACK30,DRQ30 signal
--------------------------+--------------------------------------+---------------
*1: PC-98XL model 4, PC-98XL^2 uses built-in SASI I/F.
[PC-98RL high resolution mode]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | Built-in HD I/F *1 | DACK00,DRQ00 signal
1 | Dual-use FD I/F | None
2 | Built-in HD I/F *2 | None
3 | None | DACK30,DRQ30 signal
--------------------------+--------------------------------------+---------------
*1: When DIP SW 3-3 is OFF, the built-in HD I/F uses CH#0. At this time, CH#0 cannot be used in the expansion slot.
*2: When DIP SW 3-3 is ON, the built-in HD I/F uses CH#2. At this time, CH#0 can be used in the expansion slot.
Related 0000:0484h bit 7,6
[PC-H98 High Resolution Mode]
--------------------------+--------------------------------------+---------------
DMA channel | Built-in device to be used | Expansion slot
--------------------------+--------------------------------------+---------------
0 | None | DRQ00 signal (C bus, E bus)
1 | Dual-use FD I/F | DRQ10 (E bus)
2 | None | DRQ20(E-bus)
3 | None | DRQ30 signal (C bus, E bus)
4 | None | DRQ40 (E bus)
5 | None | DRQ50 (E bus)
6 | None | DRQ60 (E bus)
--------------------------+--------------------------------------+---------------
* The DMA channel to be used for the built-in hard disk and NESA HD I/F can be set by manual setup.
* DMA channel 7 is not available.
o The I/O addresses related to DMA control are as follows.
------------+-------+-----+------------------------------------------------------
I/O address | Width | R/W | Content
------------+-------+-----+------------------------------------------------------
0001h | BYTE | R/W | Channel 0 current address register
0003h | BYTE | R/W | Channel 0 Current Word Register
0005h | BYTE | R/W | Channel 1 current address register
0007h | BYTE | R/W | Channel 1 Current Word Register
0009h | BYTE | R/W | Channel 2 current address register
000Bh | BYTE | R/W | Channel 2 Current Word Register
000Dh | BYTE | R/W | Channel 3 Current Address Register
000Fh | BYTE | R/W | Channel 3 Current Word Register
0021h | BYTE | W | DMA channel 1 bank address
0023h | BYTE | W | DMA channel 2 bank address
0025h | BYTE | W | DMA channel 3 bank address
0027h | BYTE | W | DMA channel 0 bank address
002Bh | BYTE | R/W | 32bit DMA CONTROLLER(Index)
002Dh | BYTE | R/W | 32bit DMA CONTROLLER(data)
0E05h | BYTE | W | DMA channel 0 extended bank address
0E07h | BYTE | W | DMA channel 1 extended bank address
0E09h | BYTE | W | DMA channel 2 extended bank address
0E0Bh | BYTE | W | DMA channel 3 extended bank address
------------+-------+-----+------------------------------------------------------
Related I/O 0259h,0A59h - 74h,75h
0000:0484h bit 7,6
0000:0591h
0000:05ADh bit 5
I/O 0001h,0005h,0009h,000Dh
Name Current address register setting
Target Normal, high resolution
Chip μPD8237A equivalent
Function
------------+-------+-----+-----------------------------------------------
I/O address | Width | R/W | Content
------------+-------+-----+-----------------------------------------------
0001h | BYTE | R/W | Channel 0 current address register
0005h | BYTE | R/W | Channel 1 current address register
0009h | BYTE | R/W | Channel 2 current address register
000Dh | BYTE | R/W | Channel 3 Current Address Register
------------+-------+-----+-----------------------------------------------
Description o Set the DMAC current address register (transfer start address).
o The first access handles bits 7 to 0, and the second access handles bits 15 to 8.
Related I/O 0019h
I/O 0003h,0007h,000Bh,000Fh
Name Current word register setting
Target Normal, high resolution
Chip μPD8237A equivalent
Function
------------+-------+-----+-----------------------------------------------
I/O address | Width | R/W | Content
------------+-------+-----+-----------------------------------------------
0003h | BYTE | R/W | Channel 0 Current Word Register
0007h | BYTE | R/W | Channel 1 Current Word Register
000Bh | BYTE | R/W | Channel 2 Current Word Register
000Fh | BYTE | R/W | Channel 3 Current Word Register
------------+-------+-----+-----------------------------------------------
Description o Set the DMAC current word register (number of transfers).
o The first access handles bits 7 to 0, and the second access handles bits 15 to 8.
Related I/O 0019h
I/O 0011h
Name Read status, write command
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Read status
bit 7~4: RQ3~RQ0
1=Requested
0=No request
* The bit corresponding to the DMA channel being requested is set.
bit 3～0: TC3～TC0
1=TC reached
0=TC not reached
* The bit corresponding to the DMA channel that reached TC (Terminal Count) is set.
[WRITE] Write command
bit 7: K.S.
* Set to 0 for PC-9800 (DACK active LOW)
bit 6: DS
* Set to 1 for PC-9800 (DREQ active LOW)
bit 5: WS
* Set to 0 for PC-9800 (delayed light selection)
bit 4: PR
* Set to 0 for PC-9800 (fixed priority)
bit 3: TM
* Set to 0 for PC-9800 (normal timing)
bit 2: CE
1=controller prohibited
0=controller allowed
bit 1: AH
* Set to 0 for PC-9800 (channel 0 address hold prohibited). However, since bit 0=0, this bit is actually Don't Care.
bit 0: MM
* Set to 0 for PC-9800 (memory-memory transfer prohibited)
Description o Reads the DMAC status register and writes to the command register.
Related I/O 0019h
I/O 0013h
name Write request
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Prohibited
[WRITE]
bit 7～3: Don't Care
bit 2: RB
1=request set
0=clear request
bit 1,0: CS1,CS0
11b=channel 3
10b=channel 2
01b=channel 1
00b=channel 0
Description o Sets the request bit for the specified DMA channel.
I/O 0015h
Name Write Single Mask Register Bit
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] None
[WRITE]
bit 7〜3: Don't Care
bit 2: MK
1=mask set
0=mask clear
bit 1,0: CS1,CS0
11b=channel 3
10b=channel 2
01b=channel 1
00b=channel 0
Description o Sets the mask for the specified DMA channel.
I/O 0017h
name Light mode
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Prohibited
[WRITE]
bit 7,6: MS1,MS0
* Fixed to 01b (single mode) for PC-9800
bit 5: ID
1=address decrement
0=address increment
bit 4: AT
1=Auto initialization allowed
0=Disable auto initialization
bit 3,2: TR1,TR0
11b=Forbidden
10b=Read transfer (memory → I/O)
01b=Write transfer (I/O → memory)
00b=Verify transfer
bit 1,0: CS1,CS0
11b=channel 3
10b=channel 2
01b=channel 1
00b=channel 0
Description o Specifies the transfer mode of the specified DMA channel.
I/O 0019h
Name Clear Byte Pointer Flip Flop
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Prohibited
[WRITE]
bit 7～0: Any value
Description o Clear the byte pointer flip-flop. In I/O 0001 to 000Fh, the 16-bit value is treated as lower and upper parts,
but any access to I/O 0001 to 000Fh after output to this I/O port is treated as data in the lower 8 bits.
Related I/O 0001~000Fh
I/O 001Bh
Name Read temporary register, master clear
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Read temporary register
[WRITE] Master clear
bit 7～0: Any value
Explanation o The temporary register holds the last transferred data during memory-to-memory transfer.
Since the PC-9800 does not support memory-to-memory transfers, reading this register is meaningless.
o If you output to this port (master clear), the DMAC will be in the same state as a hardware reset.
I/O 001Dh
Name Clear mask register
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Prohibited
[WRITE] Clear mask register
bit 7〜0: Don't Care
Description o Unmasks all channels.
I/O 001Fh
Name Write All Mask Register Bit
Target Normal, high resolution
Chip μPD8237A equivalent
Function
[READ] Prohibited
[WRITE] Write all mask register bit
bit 7〜4: Don't Care
bit 3～0: MB3～MB0
1=mask set
0=mask clear
Description o Set the masks for DMA channels 0 to 3 at the same time. Set the bit corresponding to each channel.
I/O 0021h,0023h,0025h,0027h
Name Bank address setting
Target Normal, high resolution
Chip DMA area
Function
------------+-------+-----+---------------------------
I/O address | Width | R/W | Content
------------+-------+-----+---------------------------
0021h | BYTE | W | DMA channel 1 bank address
0023h | BYTE | W | DMA channel 2 bank address
0025h | BYTE | W | DMA channel 3 bank address
0027h | BYTE | W | DMA channel 0 bank address
------------+-------+-----+---------------------------
*bit 7～0=A23～A16
Explanation o Since the μPD8237A is an 8-bit CPU DMAC, the DMAC itself can only control 16-bit wide addresses (64K bytes).
For this reason, the PC-9800 has an external register that allows it to handle addresses up to 24 bits wide (16 Mbytes).
o For 8086, V30, and V33 machines, only A19 to A16 (bits 3 to 0) are valid. For PC-98XA, only A22 to A16 (bits 6 to 0) are valid.
o Setting values cannot be read even if this port is read.
u When performing DMA transfer to memory space exceeding 16MB, set I/O 0E05 to 0E0Bh.
Related I/O 0029h
I/O 0439h bit 2
I/O 0E07h
I/O 0E09h
I/O 0E0Bh
I/O 0E05h
I/O 0029h
Name Bank address autoincrement mode register
Target Machines with CPU 80286 or higher
Chip DMA area
Function
[READ] None
[WRITE]
bit 7~4: set 0000b
bit 3,2: M1,M0 increment mode
11b=16MB boundary (cannot be set for PC-98XA)
10b=Setting prohibited
01b=1MB boundary
00b=64K byte boundary
bit 1,0: CS1,CS0
11b=channel 3
10b=channel 2
01b=channel 1
00b=channel 0
Description o Set the operation when the current address register (transfer address) wraps around.
o When the increment mode is on a 64K byte boundary, transfers that span physical address xxFFFFh are not possible.
If you set the increment mode to 1MB or 16MB boundaries, the bank address will be automatically incremented when the DMAC wraps around.
u The DMA bank increment boundary at startup is 64K bytes.
Related I/O 0021h,0023h,0025h,0027h
I/O 0439h
Name DMA access control etc.
Applicable to Machines equipped with 80286 or higher CPU (excluding PC-98XA)
Chip DMA area
Function
[READ/WRITE]
bit 7: Printer I/F selection ■[PC-9821Ap･As･Ae･Af･Ap2･As2･An･Ap3･As3]
■Undocumented
1=Built-in printer interface
0=98 Printer interface on high resolution board
Explanation o When the 98 Hi-Res board (PC-9821-E02) is installed on the PC-9821Ap/As/Ae/Af/Ap2/As2/An/Ap3/As3,
the built-in printer interface and the printer interface on the 98 Hi-Res board You can choose to
use either one. Normally, the printer interface on the 98 Hi-Res board is used.
u This port also exists on PC-9821Ne, Bf, Bp, Bs, Be, Xt, Xa, Xn, Xp, Xs, Xe, PC-9801BA2, BS2, BX2,
BA3, BX3, etc. If 0 is output, the built-in printer interface will be disconnected.
bit 6: Unused (?)
bit 5: Unknown ■Undocumented
bit 4: Unknown ■Undocumented
bit 3: Unused (?)
bit 2: DMA address mask register
1=Prohibit DMA access to addresses larger than 1MB
0=Allow DMA access to addresses larger than 1MB
Explanation o Set prohibition/permission of DMA transfer in a space of 1MB or more.
o The startup setting for normal mode is 1, and the startup setting for high resolution mode is 0.
bit 1: High-speed graph LIO support BIOS■[PC-9801VX21]
■Undocumented
1=use
0=don't use
bit 0: unknown ■Undocumented
■[PC-9821Ap･As･Ae･Af･Ap2･As2･An･Ap3･As3]
1=High resolution mode
0=Normal mode
Explanation: o Bits other than 2 are Undocumented.
Related 0000:0480h bit 6
I/O 002Bh,002Dh
Name 32bit DMA controller
Undocumented
Target PC-H98
Chip ORBIT
Function
------------+-------+-----+----------------------------
I/O address | Width | R/W | Content
------------+-------+-----+----------------------------
002Bh | BYTE | R/W | 32bit DMA CONTROLLER(Index)
002Dh | BYTE | R/W | 32bit DMA CONTROLLER(data)
------------+-------+-----+----------------------------
Commentary o PC-H98 has greatly expanded DMA functionality. It supports a total of 8 channels: conventional PC-9800 compatible
channels 0 to 4 and newly established channels 5 to 7. The memory space available for DMA transfer is 4GB, and the
data transfer width can be selected from 8/16/32 bits.
o The 32bit DMA controller of PC-H98 seems to be based on the DMAC part of Intel i82380 (High Performance 32bit DMA
Controller with Integrated System Support Peripherals). Added functions include μPD8237A compatibility and a DMA
peripheral circuit for PC-9800. Therefore, when accessing channels 0 to 4, conventional DMAC I/O ports can also be used.
o Specify the register number of the 32bit DMA controller with I/O 002Bh, and read and write the register with I/O 002Dh.
u For machines other than PC-H98 that can be equipped with more than 16MB of memory, the method of DMA transfer to memory
space exceeding 16MB is different from that of PC-H98.
Related 0000:0458h bit 7
I/O 0001~0029h
I/O 0E05h,0E07h,0E09h,0E0Bh
Table 32bit DMA controller register list
----------------+---------------------------------------------
Register number | Contents
----------------+---------------------------------------------
00h | DMA#0 TargetAddress(A7～A0,A15～A8)
----------------+---------------------------------------------
01h | DMA#0 ByteCount(C7～C0,C15～C8)
----------------+---------------------------------------------
02h | DMA#1 TargetAddress(A7〜A0,A15〜A8)
----------------+---------------------------------------------
03h | DMA#1 ByteCount(C7～C0,C15～C8)
----------------+---------------------------------------------
04h | DMA#2 TargetAddress(A7〜A0,A15〜A8)
----------------+---------------------------------------------
05h | DMA#2 ByteCount(C7～C0,C15～C8)
----------------+---------------------------------------------
06h | DMA#3 TargetAddress(A7〜A0,A15〜A8)
----------------+---------------------------------------------
07h | DMA#3 ByteCount(C7～C0,C15～C8)
----------------+---------------------------------------------
08h | DMA#0～3 Status/Commnad Register
----------------+---------------------------------------------
09h | DMA#0～3 Software Request Register
----------------+---------------------------------------------
0Ah | DMA#0～3 Set-Reset Mask Register
----------------+---------------------------------------------
0Bh | DMA#0～3 Mode Register I
----------------+---------------------------------------------
0Ch | DMA#0～3 Write Clear Byte-Pointer FF
----------------+---------------------------------------------
0Dh | DMA#0～3 Write DMA master clear
----------------+---------------------------------------------
0Eh | DMA#0～3 Write DMA#0～3 Clear Mask Register
----------------+---------------------------------------------
0Fh | DMA#0～3 Mask Regiser
----------------+---------------------------------------------
10h | DMA#0 Extended address bank (A31 to A24)
----------------+---------------------------------------------
11h | DMA#0 extended count (C23 to C16)
----------------+---------------------------------------------
12h | DMA#1 Extended address bank (A31 to A24)
----------------+---------------------------------------------
13h | DMA#1 extended count (C23 to C16)
----------------+---------------------------------------------
14h | DMA#2 Extended address bank (A31 to A24)
----------------+---------------------------------------------
15h | DMA#2 extended count (C23 to C16)
----------------+---------------------------------------------
16h | DMA#3 Extended address bank (A31 to A24)
----------------+---------------------------------------------
17h | DMA#3 extended count (C23 to C16)
----------------+---------------------------------------------
18h | DMA#0~3 DMA width, cycle setting
| bit 7～4: BS3,BS2,BS1,BS0
| 1111b=8bit
| 1010b=16bit
| 0101b=32bit
| Settings other than this are prohibited
| bit 3,2: TY1,TY0
| 00b=compatible cycle
| 01b=Type A
| 10b=Type B
| 11b=Reserve
| bit 1,0: DMA channel
| 00b=ch0
| 01b=ch1
| 10b=ch2
| 11b=ch3
----------------+---------------------------------------------
19h | DMA#0～3 Chaining Register
----------------+---------------------------------------------
1Ah | DMA#0～3 Commnad Regiser II
----------------+---------------------------------------------
1Bh | DMA#0～3 Mode Regiser II
----------------+---------------------------------------------
1Ch | Refresh Control Register
----------------+---------------------------------------------
75h | Refresh Wait State Register
----------------+---------------------------------------------
7Fh | DMA#4~7 Bank address auto increment mode register
| * The specification method is the same as I/O 0029h.
----------------+---------------------------------------------
89h | DMA#6 Bank (A23~A16)
----------------+---------------------------------------------
8Ah | DMA#7 Bank (A23~A16)
----------------+---------------------------------------------
8Bh | DMA#5 Bank (A23~A16)
----------------+---------------------------------------------
8Fh | DMA#4 Bank (A23~A16)
----------------+---------------------------------------------
C0h | DMA#4 Address (A7~A0),(A15~A8)
----------------+---------------------------------------------
C1h | DMA#4 count(C7~C0),(C15~C8)
----------------+---------------------------------------------
C2h | DMA#5 Address (A7~A0),(A15~A8)
----------------+---------------------------------------------
C3h | DMA#5 count (C7~C0),(C15~C8)
----------------+---------------------------------------------
C4h | DMA#6 Address (A7~A0),(A15~A8)
----------------+---------------------------------------------
C5h | DMA#6 count(C7~C0),(C15~C8)
----------------+---------------------------------------------
C6h | DMA#7 Address (A7~A0),(A15~A8)
----------------+---------------------------------------------
C7h | DMA#7 count (C7~C0),(C15~C8)
----------------+---------------------------------------------
C8h | DMA#4~7 Write command/read status
| * The specification method is the same as I/O 0011h.
----------------+---------------------------------------------
C9h | DMA#4~7 Write request
| * The specification method is the same as I/O 0013h.
----------------+---------------------------------------------
CAh | DMA#4~7 Write single mask register bits
| * The specification method is the same as I/O 0015h.
----------------+---------------------------------------------
CBh | DMA#4~7 Light mode
| * The specification method is the same as I/O 0017h.
----------------+---------------------------------------------
CCh | DMA#4~7 Clear byte pointer flip-flop
| * The specification method is the same as I/O 0019h.
----------------+---------------------------------------------
CDh | DMA#4~7 Master clear
| * The specification method is the same as I/O 001Bh.
----------------+---------------------------------------------
CEh | DMA#4~7 Clear mask register
| * The specification method is the same as I/O 001Dh.
----------------+---------------------------------------------
CFh | DMA#4~7 Write all mask register bits
| * The specification method is the same as I/O 001Fh.
----------------+---------------------------------------------
D0h | DMA#4 Extended address bank (A31 to A24)
----------------+---------------------------------------------
D1h | DMA#4 Extended count (C23 to C16)
----------------+---------------------------------------------
D2h | DMA#5 Extended address bank (A31 to A24)
----------------+---------------------------------------------
D3h | DMA#5 Extended count (C23 to C16)
----------------+---------------------------------------------
D4h | DMA#6 Extended address bank (A31 to A24)
----------------+---------------------------------------------
D5h | DMA#6 Extended count (C23 to C16)
----------------+---------------------------------------------
D6h | DMA#7 Extended address bank (A31 to A24)
----------------+---------------------------------------------
D7h | DMA#7 extended count (C23 to C16)
----------------+---------------------------------------------
D8h | DMA#4~7 DMA width, cycle setting
| bit 7～4: BS3,BS2,BS1,BS0
| 1111b=8bit
| 1010b=16bit
| 0101b=32bit
| Settings other than this are prohibited
| bit 3,2: TY1,TY0
| 00b=compatible cycle
| 01b=Type A
| 10b=Type B
| 11b=Reserve
| bit 1,0: DMA channel
| 00h=ch4
| 01h=ch5
| 10h=ch6
| 11h=ch7
----------------+---------------------------------------------
D9h | DMA#4~7 Unknown
| * Details unknown
----------------+---------------------------------------------
DBh | DMA#4~7 Unknown
| * Details unknown
----------------+---------------------------------------------
I/O 0E05h,0E07h,0E09h,0E0Bh
Name DMA Extended Bank Register
Undocumented
Target: Machines capable of mounting 16MB of memory (excluding PC-H98)
Chip DMAC peripheral
Function
------------+-------+-----+-----------------------------------------
I/O address | Width | R/W | Content
------------+-------+-----+-----------------------------------------
0E05h | BYTE | W | DMA channel 0 extended bank address
0E07h | BYTE | W | DMA channel 1 extended bank address
0E09h | BYTE | W | DMA channel 2 extended bank address
0E0Bh | BYTE | W | DMA channel 3 extended bank address
------------+-------+-----+-----------------------------------------
Explanation o Details of usage are unknown.
o Since the μPD8237A is an 8-bit CPU DMAC, the DMAC itself can only control 16-bit wide addresses (64K bytes).
For this reason, the PC-9800 was expanded to allow DMA transfer to addresses up to 24 bits wide (16 Mbytes) by
providing an external DMA bank register (I/O 0021-0029h). Models that can accommodate more than 16MB of memory
are equipped with an extended DMA bank register to further expand the address space that can be transferred by DMA.
Related I/O 0439h bit 2
I/O 0021~0029h
I/O 002Bh,002Dh